This invention relates in general to first-in first-out memory (FIFO) and in particular to high speed full and empty flag generators for FIFOs. The invention is particularly useful for integrated circuit memory devices.
A conventional FIFO includes generators for generating full and empty flag signals. An empty flag generator in a conventional FIFO includes a write counter and a read counter for counting the number of times data has been written into or read from the FIFO. The generator also includes a comparator for comparing the output of the two counters in order to determine whether the FIFO is empty or not. Many FIFOs employ counters with 10 bits or more. Thus the comparator would have to compare twenty or more inputs at the same time and is therefore slow. The conventional full flag generator has a similar structure. Thus the full and empty flag generators in conventional FIFOs are generally slow.
The full and empty flag signals are critical information for FIFO users. It is therefore preferable to provide for FIFOs full and empty flag generators that are faster than those in conventional FIFOs.